Intel 21555

8 21555 Non-Transparent PCI-to-PCI Bridge User Manual
Contents
57 Primary Interface Configuration Space Address Map ..............................................................148
58 Secondary Interface Configuration Space Address Map..........................................................148
59 Vendor ID Register ...................................................................................................................148
60 Device ID Register....................................................................................................................148
61 Primary and Secondary Command Registers ..........................................................................149
62 Primary and Secondary Status Registers.................................................................................150
63 Revision ID (Rev ID) Register ..................................................................................................151
64 Primary and Secondary Class Code Registers ........................................................................152
65 Primary and Secondary Cache Line Size Registers.................................................................152
66 Primary Latency and Secondary Master Latency Timer Registers ..........................................153
67 Header Type Register ..............................................................................................................153
68 BiST Register ...........................................................................................................................153
69 Subsystem Vendor ID Register ................................................................................................154
70 Subsystem ID Register.............................................................................................................154
71 Enhanced Capabilities Pointer Register...................................................................................154
72 Primary and Secondary Interrupt Line Registers......................................................................154
73 Primary and Secondary Interrupt Pin Registers .......................................................................155
74 Primary and Secondary Minimum Grant Registers ..................................................................155
75 Primary and Secondary Maximum Latency Registers..............................................................155
76 Device-Specific Control and Status Address Map....................................................................156
77 Chip Control 0 Register ............................................................................................................156
78 Chip Control 1 Register ............................................................................................................160
79 Chip Status Register.................................................................................................................162
80 Generic Own Bits Register .......................................................................................................164
81 I2O Outbound Post_List Status ................................................................................................165
82 I2O Outbound Post_List Interrupt Mask ...................................................................................165
83 I2O Inbound Post_List Status...................................................................................................165
84 I2O Inbound Post_List Interrupt Mask ......................................................................................166
85 I2O Inbound Queue ..................................................................................................................166
86 I2O Outbound Queue ...............................................................................................................166
87 I2O Inbound Free_List Head Pointer........................................................................................167
88 I2O Inbound Post_List Tail Pointer...........................................................................................167
89 I2O Outbound Free_List Tail Pointer........................................................................................167
90 I2O Outbound Post_List Head Pointer .....................................................................................167
91 I2O Inbound Post_List Counter ................................................................................................168
92 I2O Inbound Free_List Counter ................................................................................................168
93 I2O Outbound Post_List Counter .............................................................................................169
94 I2O Outbound Free_List Counter .............................................................................................169
95 Chip Status CSR ......................................................................................................................170
96 Chip Set IRQ Mask Register ....................................................................................................170
97 Chip Clear IRQ Mask Register .................................................................................................171
98 Upstream Page Boundary IRQ 0 Register ...............................................................................171
99 Upstream Page Boundary IRQ 1 Register ...............................................................................172
100 Upstream Page Boundary IRQ Mask 0 Register......................................................................172
101 Upstream Page Boundary IRQ Mask 1 Register......................................................................172
102 Primary Clear IRQ and Secondary Clear IRQ Registers..........................................................173
103 Primary Set IRQ and Secondary Set IRQ Registers ................................................................173
104 Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers.......................................174
105 Primary Set IRQ Mask and Secondary Set IRQ Mask Registers .............................................174
106 Scratchpad 0 Through Scratchpad 7 Registers........................................................................174