Intel 460GX - Page 12

xii Intel® 460GX Chipset System Software Developer’s Manual
10-10 Ultra DMA Timing Value Based on Drive Mode.............................................10-11
10-11 Ultra DMA/Multi Word DMA/Single Word Transfer/Mode Values ..................10-12
10-12 PIO Transfer/Mode Values.............................................................................10-12
10-13 Drive Capabilities Checklist............................................................................10-13
10-14 IFB Settings Checklist....................................................................................10-14
12-1 PCI Configuration Registers–Function 1 (IDE Interface) .................................12-1
12-2 Ultra DMA/33 Timing Mode Settings................................................................12-9
12-3 DMA/PIO Timing Values Based on IFB Cable Mode and System Speed........12-9
12-4 Interrupt/Activity Status Combinations ...........................................................12-11
13-1 PCI Configuration Registers–Function 2..........................................................13-1
13-2 Run/Stop, Debug Bit Interaction.......................................................................13-9
15-1 SERIRQ Frames ..............................................................................................15-9
15-2 RTC (Standard) RAM Bank............................................................................15-14
16-1 IFB Power States and Consumption................................................................16-1
16-2 Causes of SMI#................................................................................................16-2
16-3 Causes of SCI#................................................................................................16-3
16-4 ACPI Bits Not Implemented in IFB...................................................................16-4