Intel 460GX - 14 SM Bus Controller Configuration; SM Bus Configuration Registers (Function 3)

Intel® 460GX Chipset Software Developer’s Manual 14-1
SM Bus Controller Configuration 14
The IFB PCI Function 3 contains the SMBus Controller configuration space.
14.1 SM Bus Configuration Registers (Function 3)
Configuration
Offset
Mnemonic Register
Register
Access
00–01h VID Vendor Identification RO
02–03h DID Device Identification RO
04–05h PCICMD PCI Command R/W
06–07h PCISTS PCI Device Status R/WC
08h RID Revision Identification RO
09-0Bh CLASSC Class Code RO
0C-1Fh – Reserved –
20-23h BAR Base Address Register R/W
24–3Bh – Reserved –
2C–2Dh SVID Subsystem Vendor ID RO
2E–2Fh SID Subsystem ID RO
30–3Fh – Reserved –
3Ch IL Interrupt Line RW
3Dh IP Interrupt Pin RO
3E-3Fh – Reserved –
40h HC Host Configuration RW
41h SCOM Slave Command Port RW
42h SS1 Slave Shadow Address 1 RW
43h SS2 Slave Shadow Address 2 RW
41-FFh – Reserved –