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Intel 460GX - CLASS: Class Register; CLS: Cache Line Size; MLT: Master Latency Timer Register; HDR: Header Register

Intel 460GX
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WXB Hot-Plug
8-6 Intel® 460GX Chipset Software Developers Manual
Bits Description
7:0 Revision Identification Number
This is an 8-bit value that indicates the revision identification number for the IHPC
WXB A Steppings: Hardwired Value = 00h
WXB B0 Step: Hardwired Value = 01h
8.1.7 CLASS: Class Register
Address Offset: 09 0Bh Size: 24 bits
Default Value: 080400h Attribute: Read-Only
This register contains the Class Code for the IHPC, specifying the device function. Writes to this
register will have no effect.
Bits
Description
23:16 Base Class
This field indicates the general device category. The IHPC is a Base System Peripheral.
Hardwired Value = 08h.
15:8 Sub-Class
This field qualifies the Base Class, providing a more detailed specification of the device
function. For the IHPC this field indicates a Generic PCI Hot-Plug Controller. Hardwired
Value = 04h.
7:0 Register-level Programming Interface
This field identifies a specific programming interface (if any), that device independent
software can use to interact with the device. The Interface is not defined. Hardwired
Value = 00h.
8.1.8 CLS: Cache Line Size
Address Offset: 0Ch Size: 8 bits
Default Value: 00h Attribute: Read/Write
See PCI Specification, Rev. 2.2.
8.1.9 MLT: Master Latency Timer Register
Address Offset: 0Dh Size: 8 bits
Default Value: 00h Attribute: Read/Write
See PCI Specification, Rev. 2.2. This register is not applicable to the IHPCs within the WXB.
8.1.10 HDR: Header Register
Address Offset: 0Eh Size: 8 bits
Default Value: 00h Attribute: Read-Only
This register identifies the header layout of the configuration space. Writes to this register will have
no effect.

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