Intel 460GX - Smbslvc-Smbus Slave Command (Function 3); Smbshdw1-Smbus Slave Shadow Port 1 (Function 3); Smbshdw2-Smbus Slave Shadow Port 2 (Function 3); Smbus I;O Space Registers

SM Bus Controller Configuration
14-6 Intel® 460GX Chipset Software Developer’s Manual
14.2.13 smbslvc–SMBus Slave Command (Function 3)
Address Offset: 41h
Default Value: 00h
Attribute: Read/Write
14.2.14 smbshdw1–SMBus Slave Shadow Port 1 (Function 3)
Address Offset: 42h
Default Value: 00h
Attribute: Read/Write
14.2.15 smbshdw2–SMBus Slave Shadow Port 2 (Function 3)
Address Offset: 43h
Default Value: 00h
Attribute: Read/Write
14.3 SMBus I/O Space Registers
The “Base” address is programmed in the IFB PCI Configuration Space for Function 3, Offset 20h-
23h.
Bit Description
7:0 SMBus Host Slave Command (SMBCMD)–R/W. Specifies the command values to be
matched for SMBus master accesses to the SMBus controller host slave interface (SMBus port
10h).
Bit Description
7:0 SHDW1_ADD: Slave shadow address 1. When an SMB master generates an access to the port
defined by this register and the SHDW1_EN bit is set in I/O space, then the SHDW1_STS bit is
set and an interrupt or resume event is generated.
Bit Description
7:0 SHDW2_ADD: Slave shadow address 2. When an SMB master generates an access to the port
defined by this register and the SHDW2_EN bit is set in I/O space, then the SHDW2_STS bit is
set and an interrupt or resume event is generated.