Intel 460GX - Page 8

viii Intel® 460GX Chipset System Software Developer’s Manual
11.1.16 Deterministic Latency Control Register (Function 0)...........................11-7
11.1.17 MGPIOC–Muxed GPIO Control (Function 0) ......................................11-8
11.1.18 PDMACFG–PCI DMA Configuration Resister (Function O)................11-8
11.1.19 DDMABP–Distributed DMA Slave Base Pointer
Registers (Function 0).........................................................................11-8
11.1.20 RTCCFG–Real Time Clock Configuration Register (Function 0)........11-9
11.1.21 GPIO Base Address (Function 0)......................................................11-10
11.1.22 GPIO Enable (Function 0).................................................................11-10
11.1.23 LPC COM Decode Ranges (Function 0)...........................................11-10
11.1.24 LPC FDD/LPT Decode Ranges (Function 0) ....................................11-11
11.1.25 LPC Sound Decode Ranges (Function 0).........................................11-12
11.1.26 LPC Generic Decode Range (Function 0).........................................11-12
11.1.27 LPC Enables (Function 0) .................................................................11-13
11.2 PCI to LPC I/O Space Registers....................................................................11-15
11.2.1 DMA Registers..................................................................................11-15
11.2.2 Interrupt Controller Registers ............................................................11-20
11.2.3 Counter/Timer Registers...................................................................11-25
11.2.4 NMI Registers ...................................................................................11-28
11.2.5 Real Time Clock Registers................................................................11-29
11.2.6 Advanced Power Management (APM) Registers..............................11-30
11.2.7 ACPI Registers..................................................................................11-31
11.2.8 SMI Registers....................................................................................11-35
11.2.9 General Purpose I/O Registers .........................................................11-37
12 IDE Configuration..........................................................................................................12-1
12.1 PCI Configuration Registers (Function 1) ........................................................12-1
12.2 IDE Controller Register Descriptions (PCI Function 1) ....................................12-1
12.2.1 VID–Vendor Identification Register (Function 1).................................12-2
12.2.2 DID–Device Identification Register (Function 1) .................................12-2
12.2.3 PCICMD–PCI Command Register (Function 1)..................................12-2
12.2.4 PCISTS–PCI Device Status Register (Function 1)..............................12-3
12.2.5 CLASSC–Class Code Register (Function 1).......................................12-3
12.2.6 MLT–Master Latency Timer Register (Function 1)..............................12-4
12.2.7 BMIBA–Bus Master Interface Base Address Register
(Function 1).........................................................................................12-4
12.2.8 SVID–Subsystem Vendor ID (Function 1)...........................................12-5
12.2.9 SID–Subsystem ID (Function 1)..........................................................12-5
12.2.10 IDETIM–IDE Timing Register (Function 1)..........................................12-5
12.2.11 SIDETIM–Slave IDE Timing Register (Function 1) .............................12-6
12.2.12 DMACTL–Synchronous DMA Control Register (Function 1) ..............12-7
12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1) .............12-8
12.3 IDE Controller I/O Space Registers .................................................................12-9
12.3.1 BMICx–Bus Master IDE Command Register (I/O) ..............................12-9
12.3.2 BMISx–Bus Master IDE Status Register (I/O)...................................12-10
12.3.3 BMIDTPx–Bus Master IDE Descriptor Table Pointer Register (I/O) .12-11
13 Universal Serial Bus (USB) Configuration.....................................................................13-1
13.1 PCI Configuration Registers (Function 2) ........................................................13-1
13.2 USB Host Controller Register Descriptions (PCI Function 2) ..........................13-2
13.2.1 VID–Vendor Identification Register (Function 2).................................13-2
13.2.2 DID–Device Identification Register (Function 2) .................................13-2
13.2.3 PCICMD–PCI Command Register (Function 2)..................................13-2