49
USWC Write Post
Set this option to Enabled to allow write operations from USWC memory to be posted. The
settings are Enabled and Disabled. The Optimal default setting is Enabled.
Master Latency Timer (Clks)
The settings are Disabled, 32, 64, 96, 128, 160, 192, and 224. The Optimal default setting is
64.
Multi-Trans Timer (Clks)
The settings are Disabled, 32, 64, 96, 128, 160, 192, and 224. The Optimal default setting is
32.
PCI1 to PCI0 Access
The Optimal default setting is Disabled.
Method of Memory Detection
Settings are Auto & SPD and Auto Only. The Optimal default setting is Auto & SPD.
DRAM Integrity Mode
The settings are None, EC, and ECC Hardware. The Optimal default setting is ECC
Hardware.
DRAM Refresh Rate
The settings are 15.6 us, 31.2 us, 62.4 us, 124.8 us, and 249.6 us. The Optimal default
setting is 15.6 us.
Memory Hole
This option specifies the location of an area of memory that cannot be addressed on the ISA
bus. The settings are Disabled, 15 MB-16 MB, and 512KB-640KB. The Optimal default
setting is Disabled.
To Next Page
Loading...
