Kirisun DP485 User Manual

DP485 Service Manual
10
4.7.2.Port Description of AT1846S
AVDD
1
Power supply
SCLK
2
Clock input for serial control bus
SDIO
3
Data input/output for serial control bus
AVDD
4
Power supply
XTAL1
5
Oscillator pin 1
XTAL2
6
Oscillator pin 2,control interface select
MODE
7
When MODE = VL, I2C Interface is select; When MODE = VH, SPI Interface is
select
SENB
8
Latch enable (active low) input for serial control bus
AFOUT
9
Audio signal output to speaker
NC*
10
No connection
MIC_IN
11
MIC input
Cc
12
Compensation capacitor connection
AVDD
13
Power supply
NC*
14
No connection
RFIN
15
RF signal input
AVDD
16
Power supply
NC*
17
No connection
RFOUT
18
RF signal output
NC*
19
No connection
NC*
20
No connection
AVDD
21
Power supply
PABIAS
22
PA bias supply for PA
AVDD
23
Power supply
PDN
24
Chip enable, high active; Chip sleep, low active

Kirisun DP485 Specifications

General

Frequency	136~174 MHz, 400~470 MHz
Channel Capacity	256 channels
Channel Spacing	25 kHz/12.5kHz
Antenna Impedance	50Ω
Operating Voltage	7.4V
Rated Power	1W 16Ω
Transmitting Power	4W/1W@7.4V DC
Current Consumption	≤1.5A@ 7.4V DC
Working Temperature	-25℃~ +55℃
Microphone Impedance	2.2kΩ
Battery	Lithium-ion battery DC 7.4V , 2000mAh
Receiving Sensitivity (12dB SINAD )	-120dBm
Squelch Sensitivity (3-level)	≤-120dBm
Selectivity of Adjacent Channels	70dB@25KHz /60dB@12.5KHz
Intermodulation Immunity	65dB@25KHz/12.5 KHz
Blocking	84dB
Frequency Stability	≤±2.5ppm
Maximum Modulation Offset	±5kHz@25KHz /±2.5kHz@12.5KHz
Modulation Distortion	≤3%
Spurious Emission	≤-36dBm