Marantz CD6005 - Page 62

AK4104 (IC104)
AK4104 Terminal Function
Block Diagram
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 3 -
AK4104ET 20 +85 C 16pin TSSOP (0.65mm pitch)
AKD4104 AK4104
1
MCLK
LRCK
BICK
CSN
CCLK
CDTI
AK4104
Top
View
2
3
4
5
6
7
8
TX
VDD
CDTO/ SDTI2
VSS
TEST4
TEST3
TEST2
16
15
14
13
12
11
10
9
PDN
SDTI1
TEST1
ASAHI KASEI [AK4104]
MS0642-J-01 2010/09
- 4 -
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
2 BICK I Audio Serial Data Clock Pin
3 SDTI1 I Audio Serial Data Input 1 Pin
4 LRCK I Input Channel Clock Pin
5 PDN I
Power Down and Reset Pin
L: Power down and Reset, H: Power up
6 CSN I Chip Select Pin
7 CCLK I Control Data Clock Pin
8 CDTI I Control Data Input Pin
9 TEST1 I
TEST Pin
This pin should be connected to VDD.
10 TEST2 O
TEST Pin
This pin should be OPEN.
11 TEST3 O
TEST Pin
This pin should be OPEN.
12 TEST4 O
TEST Pin
This pin should be OPEN.
13 VSS - Ground Pin
14 VDD -
Power Supply Pin, 2.7
3.6V
CDTO O Control Data Output Pin, The output is Hi-Z when PDN pin = L.
15
SDTI2 I Audio Serial Data Input 2 Pin
16 TX O
Transmit Channel Output Pin, The output is L when PDN pin = L or RSTN bit
=0 or PW bit = 0 or MCLK stops.
[AK4104]
MS0642-J-01 2010/09
- 2 -
LRCK
BICK
Audio
Data
Interface
MCLK
PDN
Prescaler
Biphase
Encoder
SDTI1
TX
CDTO
CSN
CCLK
CDTI
µP
Interface
VDD
VSS
Figure 1. AK4104 Block Diagram (MODE bit = 0)
LRCK
BICK
Audio
Data
Interface
MCLK
PDN
Prescaler
Biphase
Encoder
SDTI1
TX
CSN
CCLK
CDTI
µP
Interface
VDD
VSS
SDTI2
Figure 2. AK4104 Block Diagram (MODE bit = 1)
62