34
3.2 THEORY OF OPERATION
The Field I/O module provides the interface between the controller and the external world, so that it
contains all hardware and software needed for performing its functions as established into the TEES 2009
and Errata 2 from December 5
th
2014.
The module contains a processor, SRAM, FLASH, parallel input/output ports, muzzle jumper, serial
communication circuitry, C1S, C11S and C12S connectors installed on the front panel plate; serial
communication circuitry, power Supply (+12VDC and +5VDC); and required software.
Processor
It is a Freescale MC68LC302 Integrated Multiprotocol Processor; it has a static 68008 core and a flexible
communications architecture. The processor is running at 20MHz generated by an external oscillator.
Memory
SRAM
The 4Mbit Static RAM is used to execute code, store and retrieve all variable and temporary data.
It uses an 18-bit address bus (A0 to A17) and a 16-bit data bus (I/O 0 to I/O 15).
There is a glue logic stage to decode the signals from the control bus and handle the SRAM; this stage
receives the signals and generates the proper signals for enabling the SRAM, for selecting the read/write
operations and for selecting the low byte or upper byte.
FLASH
A 4Mbit FLASH memory is used in order to store the firmware. It is a non-volatile memory and serves as
a media for storing program code and nonvolatile data so that if power is removed the stored data is not
lost.
It uses an 18-bit address bus (A0 to A17) and a 16-bit data bus (I/O 0 to I/O 15).
Control signals
The control signals POWERUP, POWERDOWN and LINESYNC are signals coming from the Power
Supply and are generated according to the conditions of the AC input power; CPURESET is a signal
coming from the CPU and it is a software reset. They are received through the A3 slot; all are inverted
and isolated before using them as follow:
POWERUP and CPURESET:
These signals are OR’ed at the isolation stage, resulting into the NRESET signal.
It enables a buffer gate to generate a reset signal that goes to the microprocessor and FLASH
memory.
It is converted to EIA-485 differential signals and routed to the C12S connector.
To Next Page
Loading...
Need help?
General
