SmartFusion2 SoC FPGA - Cache Controller Configuration - Libero SoC v11.7
16 Revision 10
Appendix: Design and Programming Files
Download the design files from the Microsemi SoC Products Group website:
http://soc.microsemi.com/download/rsc/?f=m2s_ac389_liberov11p7_df
The design file consists Libero SoC Verilog project, SoftConsole software project, and programming
files (*.stp) for the SmartFusion2 Security Evaluation Kit board. Refer to the
Readme.txt file included in
the design file for the directory structure and description.
Download the programming files from the Microsemi SoC Products Group website:
http://soc.microsemi.com/download/rsc/?f=m2s_ac389_liberov11p7_pf
The programming file consists STAPL programming file (*.stp) for the SmartFusion2 Security Evaluation
Kit board.
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