SmartFusion2 SoC FPGA - Cache Controller Configuration - Libero SoC v11.7
2 Revision 10
To aid in system reliability, the instruction cache is constructed of single event upset (SEU) tolerant
latches. This application note describes the configuration of cache controller for various cacheable
memories.
Design Requirements
Table 1 shows the design requirements.
Note: *For this application note, SoftConsole v3.4 SP1 is used. For using SoftConsole v4.0, see the
TU0546: SoftConsole v4.0 and Libero SoC v11.7 Tutorial.
Table 1 • Design Requirements
Design Requirements Description
Hardware Requirements
SmartFusion2 Security Evaluation Kit
• 12 V adapter
• FlashPro4 programmer
• USB A to Mini-B USB cable
Note: Refer the UG0594: SmartFusion2 Security
Evaluation Kit User Guide for more information
Rev D or later
Host PC or Laptop • Windows XP SP2 Operating System - 32-bit or 64-bit
• Windows 7 Operating System - 32-bit or 64-bit
Software Requirements
Libero
®
System-on-Chip (SoC) v11.7
SoftConsole v3.4 SP1*
Host PC Drivers USB to UART drivers
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