Microsemi SmartFusion2 - Smartfusion2 Cache Controller Features

SmartFusion2 SoC FPGA - Cache Controller Configuration - Libero SoC v11.7
6 Revision 10
SmartFusion2 Cache Controller Features
The following sections explain the various user configurable features of the cache controller in the
SmartFusion2 device:
• Cache Memory Enable or Disable
• Cache Flush
• Cache Locked Mode
Cache Memory Enable or Disable
Cache memory can be enabled or disabled dynamically by using the CC_CR system register.
Instructions are cached when the cache memory is enabled. In Cache Disabled mode, all transactions
are treated as non-cacheable.
Use the following steps to enable or disable the cache memory dynamically using the application code:
1. Set the cacheable region.
2. Enable cache memory.
3. Run the task.
4. Get the cache status information.
5. Disable cache memory.
Refer to Table 4 on page 11 for APIs to enable or disable cache memory and to get cache status
information.
Cache Flush
Cache memory can be flushed in the following two ways:
• Complete cache memory flush: When you flush the full cache memory, all the cached instructions
are deleted.
• Index based cache memory flush: When you flush one index in the cache memory, it invalidates
all tags of four sets at one index only.
The following steps describe how to flush the cache memory:
1. Enable cache memory.
2. Run the task (the instructions are cached).
3. Disable cache memory.
4. Flush the cache memory (the cached instructions are deleted).
Refer to Table 4 on page 11 for APIs to flush the cache memory.
Cache Locked Mode
The Cache Locked mode is a special mode that provides predictable execution, which is a requirement
for some specific applications. Before enabling the Cache Locked mode, the software ensures that the
code is copied to cache memory by simulating a sequential location cache miss through I-code. After
copying the complete 8 KB of data, the Cache Locked mode is enabled. After the Cache Locked mode is
enabled, any access from 0 to 8 KB is directly read from the cache and the cache is not invalidated or
refilled for normal operations. Memory region beyond 8 KB is treated as non-cacheable and accessed as
per the memory map.
The Cache Locked mode can only be used with either DDR or eNVM memory and the lock base address
must be in the Cortex-M3 processor code region. The code image that is copied to cache memory is also
present in eNVM or DDR memory. After executing the code from the cache, the execution control comes
to the main memory to execute the remaining code image. You can enable or disable the Cache Locked
mode dynamically.