SmartFusion2 SoC FPGA - Cache Controller Configuration - Libero SoC v11.7
Revision 10 17
List of Changes
The following table shows the important changes made in this document for each revision.
Revision Changes Page
Revision 10
(March 2016)
Updated the document for Libero SoC v11.7 software release (SAR 76876). N/A
Revision 9
(October 2015)
Updated the document for Libero SoC v11.6 software release (SAR 71810). N/A
Revision 8
(February 2015)
Updated the document for Libero SoC v11.5 software release (SAR 64751). N/A
Revision 7
(October 2014)
Updated the document for Libero SoC v11.4 software release (SAR 61633). N/A
Revision 6
(May 2014)
Updated the document for Libero SoC v11.3 software release (SAR 57102). N/A
Revision 5
(November 2013)
Updated the document for Libero SoC v11.2 software release (SAR 52966). N/A
Revision 4
(November 2013)
Updated note (SAR 51331). 10
Updated Figure 5 and Figure 6 (SAR 51331). 8, 9
Updated Table 5 and Table 6 with latest version of s/w v11.1 SP2 and the latest
silicon Rev D (SAR 51331).
12
Deleted Jumper J2 from the Table 5 (SAR 51331). 12
Revision 3
(May 2013)
Updated the document for Libero SoC v11.0 software release (SAR 47616). N/A
Revision 2
(March 2013)
Updated for Libero SoC v11.0 beta SP1 release (SAR 45274). N/A
Revision 1
(November 2012)
Modified "Remapping eNVM as Cacheable Region" section (SAR 42936). 4
Modified "Remapping of External RAM as Cacheable Region" section (SAR 42936). 5
Modified "Cache Flush" section (SAR 42936). 6
Modified "Software Implementation" section (SAR 42936). 10
Modified "Running the Design" section (SAR 42936). 11
Updated Figure 9, Figure 13 and Figure 14 (SAR 42936). 13, 15
Modified "Conclusion" section (SAR 42936). 15
Modified "Appendix: Design and Programming Files" section (SAR 42936). 16