SmartFusion2 SoC FPGA - Cache Controller Configuration - Libero SoC v11.7
Revision 10 9
MMUART_1 is routed through the FPGA fabric for communicating with the serial terminal program.
MDDR is configured for LPDDR at 80 MHz speed. Figure 6 shows MSS MDDR configuration settings.
Click Import Configuration to import the register configuration for LPDDR (refer to "Appendix: Design
and Programming Files" on page 16 for DDR configuration file).
Figure 6 • MSS External Memory Configurator
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