15
8575
8575
N/B Maintenance
N/B Maintenance
1.2.2.2 DDR buffer frequency synthesizer_ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application:
Low skew, low jitter PLL clock driver
I
2
C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
SiS645/650 style chipsets
Product description/features:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz): <120ps
CYCLE - CYCLE jitter (>100MHz): <65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
Switching Characteristics
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