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N/B Maintenance
N/B Maintenance
The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in
a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The
transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23,
TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42 or TSB12LV01A.
1.2.6 TSB41AB1, IEEE 1394a One-Port Cable Transceiver/Arbiter
The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide
the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-
MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for
resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD
terminal high, stops operation of the PLL.
The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO\ input
terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal
differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive
or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-
2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation
the ISO/terminal on the PHY must be high.
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