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8575
8575
N/B Maintenance
N/B Maintenance
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB1 automatically enters a low-
power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB1 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB1 exits the low-power mode when the LPS input is asserted high or when a
port event occurs which requires that the TSB41AB1 become active in order to respond to the event or to
notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is
detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output
becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is
asserted high when the TSB41AB1 is in the low-power mode.
The LPS input is considered inactive if it remains low for more than 2.6 us and is considered active otherwise.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than 26 us, the PHY-LLC interface is
put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface
is also held in the disabled state during hardware reset. The TSB41AB1 continues the necessary repeater
functions required for normal network operation regardless of the state of the PHY-LLC interface. When the
interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and
returns it to normal operation.
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