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MELSEC-Q
2 SYSTEM CONFIGURATION
2.2.3 List of functions for each CPU module
The available functions of the MELSECNET/H depend on the CPU module with which
a network module is mounted.
1)High Performance model QCPU, Process CPU
2)Basic model QCPU
3)Redundant CPU
4)Universal model QCPU
5)Safety CPU
Function
CPU module
Reference
section
1) 2) 3) 4) 5)
Cyclic transmission function
Section 3.2.1
MELSECNET/H Extended mode
Section 5.1
Refresh parameter
*1
*1
Section 5.7
Common parameter
*2
*2
Section 5.3
Station inherent parameter
Section 5.6
Inter-link data transfer function
*5*8
Section 7.2
Designation of I/O master station
Section 5.3.3
Designation of reserved station
Section 5.3.4
Low-speed cyclic transmission function
*5*8
Section 7.3
Redundant system function
Section 7.10
Transient transmission function
Section 7.4
Routing function
*1
*1
Section 7.4.2
Group function
Section 7.4.3
Message sending function using logical channel numbers
Section 7.4.4
Link dedicated instruction
*3
*3*6
Section 7.4.5
RAS function Section 3.2.2
Automatic return function
Section 3.2.2
Control station shift function
Section 3.2.2
Control station return control function
Section 3.2.2
Loopback function
Section 3.2.2
Station detach function
Section 3.2.2
Transient transmission possible even in case of CPU error
Section 3.2.2
Confirmation of transient transmission error detection time
Section 3.2.2
Module diagnosis
Section 3.2.2
Network test
*7
*5
*7
Section 7.8
Network diagnosis
Section 8.1
Direct accessing of link device
Section 7.1
Clock setting to a station on the network by GX Developer
Section 7.4.6
Getting the interrupt sequence program started
*4
Section 7.5
Multiplexed transmission function
Section 7.6
Simplified redundant setting of network
Section 7.7
Increasing the number of send points by connecting multiple
modules of the same network number
Section 7.9
: Available, : Unavailable
*1: Up to 8 modules can be set.
*2: The low-speed LB/LW cannot be set because these models do not support the low-speed cyclic transmission function.
*3: The SREAD/SWRITE instruction’s read/write notice device (D3) becomes invalid. (The same operation as the
READ/WRITE instructions takes place.)
*4: It is available for the Basic model QCPU of function version B or later.
*5: Available for the Universal model QCPU whose serial No. (first 5 digits) is "09042" or later.
*6: For link dedicated instructions for the safety CPU, refer to Section 6.3.
*7: Basic model QCPU and safety CPU cannot execute a network test on a sequence program.
*8: Applicable to the Universal model QCPU excluding the Q00UJCPU, Q00UCPU, and Q01UCPU.
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