Mitsubishi Electric Q26UD(E)HCPU - Page 518

516
SD52 Battery low
Bit pattern
indicating
where
battery
voltage drop
occurred
• This register has the same bit pattern as that of SD51.
• After an alarm is detected (the alarm bit turns on), the alarm
bit turns off if an error is detected (the error bit turns on).
(Universal model QCPU only, except the QnUDVCPU)
• This register stores "0" (turns off) when the battery voltage
returns to normal.
S (Error) New
QCPU
LCPU
SD53
AC/DC
DOWN
detection
Number of
times for
AC/DC
DOWN
detection
• A value stored in this register is incremented by 1 whenever
the input voltage falls to or below 85% (AC power)/65% (DC
power) of the rating during operation of the CPU module.
• The counter repeats increment and decrement of the value;
0  32767  -32768  0
S (Error) D9005
QCPU
LCPU
SD60
Number of
module with
blown fuse
Number of
module with
blown fuse
This register stores the lowest I/O number of the module with
a blown fuse.
S (Error) D9000
QCPU
LCPU
*9
SD61
I/O module
verify error
number
I/O module
verify error
module
number
This register stores the lowest I/O number of the module
where the I/O module verify error has occurred.
S (Error) D9002
QCPU
LCPU
SD62
Annunciator
number
Annunciator
number
This register stores the number of the annunciator (F number)
detected first.
S
(Instruction
execution)
D9009
QCPU
LCPU
SD63
Number of
annunciators
Number of
annunciators
This register stores the number of detected annunciators.
S
(Instruction
execution)
D9124
QCPU
LCPU
SD64
Table of
detected
annunciator
numbers
Annunciator
detection
number
When an annunciator (F) is turned on by the OUT F or SET F
instruction, the F numbers are stored from SD64 to SD79 in
chronological order.
The number of an annunciator (F) turned off by the RST F
instruction is deleted from SD64 to SD79, and F numbers
stored later than the register where the deleted F number was
stored are shifted upward.
When the LEDR instruction is executed, the contents of SD64
to SD79 are shifted upward by 1. After 16 annunciators have
been detected, detection of the 17th will not be stored from
SD64 through SD79.
S
(Instruction
execution)
D9125
QCPU
LCPU
SD65 D9126
SD66 D9127
SD67 D9128
SD68 D9129
SD69 D9130
SD70 D9131
SD71 D9132
SD72
New
SD73
SD74
SD75
SD76
SD77
SD78
SD79
SD80 CHK number CHK number
Error codes detected by the CHK instruction are stored as
BCD code.
S
(Instruction
execution)
New
Qn(H)
QnPH
QnPRH
Number Name Meaning Explanation
Set by
(When Set)
Corresponding
ACPU
D9
Corresponding
CPU
(Number
detected)
(Number of
annunciators
detected)
(Number
detected)
SD62
SD63
0505050505050
012 3 234
0505050505050
SD64
SD65
SD66
SD67
SD68
SD69
SD70
SD71
SD72
SD73
SD74
SD75
SD76
SD77
SD78
SD79
0 0 25 25 99 99 99
0009901515
000 0 0070
000 0 000
000 0 000
000 0 000
0
0
000000
000000
000 0 000
000 0 000
000 0 000
000 0 000
000 0 000
000 0 000
000 0 000
50
5
50
99
15
70
65
0
0
0
0
0
0
0
0
0
0
0
99
4
99
15
70
65
0
0
0
0
0
0
0
0
0
0
0
0
LEDR
SET
F50
SET
F25
SET
F99
RST
F25
SET
F15
SET
F70
SET
F65