Mitsubishi MELSEC QCPU - 16-Bit and 32-Bit Negation Transfers (CML, CMLP, DCML, DCMLP)

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MELSEC-Q/QnA
6 BASIC INSTRUCTIONS
High Performance
QnA Q4AR
Basic
QCPU
PLC CPU
Process CPU
6.4.4 16-bit and 32-bit negation transfers (CML, CMLP, DCML, DCMLP)
Usable Devices
Internal Devices
(System, User)
MELSECNET/10(H)
Direct J
\
Set
Data
Bit Word
File
Register
Bit Word
Special
Function
Module
U
\G
Index
Register
Zn
Constant
K, H
Other
S
D
[Instruction Symbol] [Execution Condition] indicates CML or DCML
Command
Command
P
CML, DCML
CMLP, DCMLP
S D
S D
[Set Data]
Set Data Meaning Data Type
S
Data to be inverted, or number of device storing this data
D
Number of device that will store results of inversion
BIN 16/32 bits
[Functions]
CML
(1) Inverts 16-bit data designated by
S
bit by bit, and transfers the result to the device designated
by
D
.
b15
1Before execution 0
1 1 0 1 0 0 0 1 1 1 0 0 10
b0
b15
1
1 1 1 1 1 1 1
b0
A
fter execution
Inversion
0000 000 0
S
D
DCML
(1) Inverts 32-bit data designated by
S
bit by bit, and transfers the result to the device designated
by
D
.
1Before execution
0
1 1
0
1
0 0 0
1 11
0 0
1
0
Inversion
b15 b0 b0b15
After execution
1
1 1 1 1 1 1 1
b15 b0 b0b15
+1
+1
0000 0000
S
D
S
S
D
D
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