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MELSEC-Q/QnA
6 BASIC INSTRUCTIONS
High Performance
QnA Q4AR
Basic
QCPU
PLC CPU
Process CPU
6.4.7 16-bit and 32-bit data exchanges (XCH, XCHP, DXCH, DXCHP)
Usable Devices
Internal Devices
(System, User)
MELSECNET/10(H)
Direct J
\
Set
Data
Bit Word
File
Register
Bit Word
Special
Function
Module
U
\G
Index
Register
Zn
Constant
K, H
Other
D1
D2
[Instruction Symbol] [Execution Condition] indicates XCH/DXCH
Command
Command
P
D1 D2
D1 D2
XCH, DXCH
XCHP, DXCHP
[Set Data]
Set Data Meaning Data Type
D1
D2
Head number of device storing data to be exchanged BIN 16/32 bits
[Functions]
XCH
(1) Conducts 16-bit data exchange between
D1
and
D2
.
b7 b0b15 b8
Before execution
After execution
0000011100001110
1111000000001111 0000011100001110
1111000000001111
D1
D2
b7 b
b15 b8
b7
b
b15 b8
b7
b0
b15 b8
D1
D2
DXCH
(1) Conducts 32-bit data exchange between
D1
+1,
D1
and
D2
+1,
D2
.
Before execution
fter execution
+1
b15 b0
+1
b31 b16
+1+1
111 1111111
0000
111 00000001111
111 11111110000
111
0000000
1111
D1
D2D1 D2
b15 b0b31 b16
b15 b0b31 b16
b15 b0b31 b16
D2 D2D1 D1
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