EasyManuals Logo
Home>Mitsubishi>Controller>MELSEC QCPU

Mitsubishi MELSEC QCPU User Manual

Mitsubishi MELSEC QCPU
285 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #8 background imageLoading...
Page #8 background image
A - 6 A - 6
6.3.7 Conversion from BIN 16 and 32-bit data to Gray code (GRY, GRYP, DGRY, DGRYP)...............6 - 67
6.3.8 Conversion of Gray code to BIN 16 and 32-bit data (GBIN, GBINP, DGBIN, DGBINP) ...............6 - 69
6.3.9 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG, NEGP, DNEG, DNEGP)......6 - 71
6.3.10 Sign reversal for floating decimal point data (ENEG, ENEGP) .................................................... 6 - 73
6.3.11 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD, BKBCDP)........................ 6 - 74
6.3.12 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN, BKBINP).................. 6 - 76
6.4 Data Transfer Instructions......................................................................................................................6 - 78
6.4.1 16-bit and 32-bit data transfers (MOV, MOVP, DMOV, DMOVP)..................................................6 - 78
6.4.2 Floating decimal point data transfers (EMOV, EMOVP) ................................................................6 - 80
6.4.3 Character string transfers ($MOV, $MOVP)................................................................................... 6 - 82
6.4.4 16-bit and 32-bit negation transfers (CML, CMLP, DCML, DCMLP)..............................................6 - 84
6.4.5 Block 16-bit data transfers (BMOV, BMOVP).................................................................................6 - 87
6.4.6 Identical 16-bit data block transfers (FMOV, FMOVP) ................................................................... 6 - 89
6.4.7 16-bit and 32-bit data exchanges (XCH, XCHP, DXCH, DXCHP)................................................. 6 - 91
6.4.8 Block 16-bit data exchanges (BXCH, BXCHP)............................................................................... 6 - 93
6.4.9 Upper and lower byte exchanges (SWAP, SWAPP)......................................................................6 - 95
6.5 Program Branch Instruction ................................................................................................................... 6 - 96
6.5.1 Pointer branch instructions (CJ, SCJ, JMP)....................................................................................6 - 96
6.5.2 Jump to END (GOEND) ..................................................................................................................6 - 99
6.6 Program Execution Control Instructions ..............................................................................................6 - 100
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI, EI IMASK) ............................6 - 100
6.6.2 Recovery from interrupt programs (IRET) ....................................................................................6 - 109
6.7 I/O Refresh Instructions .......................................................................................................................6 - 111
6.7.1 I/O Refresh (RFS, RFSP)..............................................................................................................6 - 111
6.8 Other Convenient Instructions..............................................................................................................6 - 113
6.8.1 Count 1-phase input up or down (UDCNT1).................................................................................6 - 113
6.8.2 Counter 2-phase input up or down (UDCNT2) .............................................................................6 - 115
6.8.3 Teaching timer (TTMR).................................................................................................................6 - 117
6.8.4 Special function timer (STMR) ......................................................................................................6 - 119
6.8.5 Rotary table near path rotation control (ROTC)............................................................................6 - 122
6.8.6 Ramp signal (RAMP).....................................................................................................................6 - 124
6.8.7 Pulse density measurement (SPD)...............................................................................................6 - 126
6.8.8 Fixed cycle pulse output (PLSY) ...................................................................................................6 - 128
6.8.9 Pulse width modulation (PWM).....................................................................................................6 - 130
6.8.10 Matrix input (MTR).......................................................................................................................6 - 132
7. APPLICATION INSTRUCTIONS 7 - 1 to 7 - 332
7.1 Logical Operation Instructions................................................................................................................ 7 - 2
7.1.1 Logical products with 16-bit and 32-bit data (WAND, WANDP, DAND, DANDP) ........................ 7 - 3
7.1.2 Block logical products (BKAND, BKANDP) ....................................................................................7 - 8
7.1.3 Logical sums of 16-bit and 32-bit data (WOR, WORP, DOR, DORP)........................................... 7 - 10
7.1.4 Block logical sum operations (BKOR, BKORP)..............................................................................7 - 14
7.1.5 16-bit and 32-bit exclusive OR operations (WXOR, WXORP, DXOR, DXORP)..........................7 - 16
7.1.6 Block exclusive OR operations (BKXOR, BKXORP)...................................................................... 7 - 20
7.1.7 16-bit and 32-bit data non-exclusive logical sum operations
(WXNR, WXNRP, DXNR, DXNRP)................................................................................................7 - 22
7.1.8 Block non-exclusive logical sum operations (BKXNR, BKXNRP).................................................. 7 - 28
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Mitsubishi MELSEC QCPU and is the answer not in the manual?

Mitsubishi MELSEC QCPU Specifications

General IconGeneral
BrandMitsubishi
ModelMELSEC QCPU
CategoryController
LanguageEnglish

Related product manuals