On-Chip Cache Memories
MOTOROLA
MC68030 USER’S MANUAL
6-7
6.1.2.1 WRITE ALLOCATION.
The supervisor program can configure the data cache for
either of two types of allocation for data cache entries that miss on write cycles. The state
of the write allocation (WA) bit in the cache control register specifies either no write
allocation or write allocation with partial validation of the data entries in the cache on writes.
When no write allocation is selected (WA=0), write cycles that miss do not alter the data
cache contents. In this mode, the processor does not replace entries in the cache during
write operations. The cache is updated only during a write hit.
When write allocation is selected (WA=1), the processor always updates the data cache on
cachable write cycles, but only validates an updated entry that hits or an entry that is
updated with long-word data that is long-word aligned. When a tag miss occurs on a write
of long-word data that is long-word aligned, the corresponding tag is replaced, and only the
long word being written is marked as valid. The other three entries in the cache line are
invalidated when a tag miss occurs on a misaligned long-word write or on a byte or word
write, the data is not written in the cache, the tag is unaltered, and the valid bit(s) are cleared.
Thus, an aligned long-word data write may replace a previously valid entry; whereas, a
misaligned data write or a write of data that is not long word may invalidate a previously valid
entry or entries.
Figure 6-3. On-Chip Data Cache Organization
DATA FROM DATA
CACHE DATA BUS
CACHE CONTROL LOGIC
DATA TO
EXECUTION UNIT
F F F
CCC 3 222211111111110000000000
210 1 32 01 987 65432109876543210
COMPARATOR
TAG
1 OF 16
SELECT
VALID
TAG REPLACE
INDEX
TAG
LINE HIT
V V VV
ACCESS ADDRESS
ENTRY HIT
A
LONG-WORD
SELECT
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
AAAAAAAAAAAAAAAAAAAAAAAA
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