Motorola MC68030 User Manual

Bus Operation
7-22 MC68030 USER’S MANUAL MOTOROLA
7.2.4 Address, Size, and Data Bus Relationships
The data transfer examples show how the MC68030 drives data onto or receives data from
the correct byte sections of the data bus. Table 7-7 shows the combinations of the size
signals and address signals that are used to generate byte enable signals for each of the
four sections of the data bus for noncachable read cycles and all write cycles if the
addressed device requires them. The port size also affects the generation of these enable
signals as shown in the table. The four columns on the right correspond to the four byte
enable signals. Letters B, W, and L refer to port sizes: B for 8-bit ports, W for 16-bit ports,
and L for 32-bit ports. The letters B, W, and L imply that the byte enable signal should be
true for that port size. A dash (—) implies that the byte enable signal does not apply.
The MC68030 always drives all sections of the data bus because, at the start of a write
cycle, the bus controller does not know the port size. The byte enable signals in the table
apply only to read operations that are not to be internally cached and to write operations.
For cachable read cycles, during which the data is cached, the addressed port must drive
all sections of the bus on which it resides.
Figure 7-17. Misaligned Cachable Long-Word Transfer from Long-Word Bus
MC68EC030
SIZ1 SIZ0 A2 A1
0 0 0 1 1
1 1 1 0 0
A0
MEMORY CONTROL
DSACK1 DSACK0
L
LL
OP0 OP1
31 0LONG WORD OPERAND (REGISTER)
DATA BUS
D31 D0
LONG WORD MEMORY
MSB UMB
PR2
OP1 OP2
PR1
OP2 OP3
PR
OP3
OP0
N
LMB LSB
L
PR2 PR1
31 0CACHE ENTRIES
PR OP0
OP1 OP2
31 0
OP3 N

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English