Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-27
7.2.8 Asynchronous Operation
The MC68030 bus may be used in an asynchonous manner. In that case, the external
devices connected to the bus can operate at clock frequencies different from the clock for
the MC68030. Asynchronous operation requires using only the handshake line (AS
, DS,
DSACK1
, DSACK0, BERR, and HALT) to control data transfers. Using this method, AS
signals the start of a bus cycle, and DS
is used as a condition for valid data on a write cycle.
Decoding the size outputs and lower address lines (A0 and A1) provides strobes that select
the active portion of the data bus. The slave device (memory or peripheral) then responds
by placing the requested data on the correct portion of the data bus for a read cycle or
latching the data on a write cycle, and asserting the DSACK1
/DSACK0 combination that
corresponds to the port size to terminate the cycle. If no slave responds or the access is
invalid, external control logic asserts the BERR
or BERR and HALT signal(s) to abort or retry
the bus cycle, respectively.
The DSACK
x signals can be asserted before the data from a slave device is valid on a read
cycle. The length of time that DSACK
x may precede data is given by parameter #31, and it
must be met in any asynchronous system to insure that valid data is latched into the
processor. (Refer to MC68030EC/D,
MC68030 Electrical Specifications
for timing
parameters.) Notice that no maximum time is specified from the assertion of AS
to the
assertion of DSACKx
. Although the processor can transfer data in a minimum of three clock
cycles when the cycle is terminated with DSACKx
, the processor inserts wait cycles in clock
period increments until DSACKx
is recognized.
The BERR
and/or HALT signals can be asserted after the DSACKx signal(s) is asserted.
BERR
and/or HALT must be asserted within the time given as parameter #48, after DSACKx
is asserted in any asynchronous system. If this maximum delay time is violated, the
processor may exhibit erratic behavior.
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