Bus Operation
MOTOROLA MC68030 USER’S MANUAL 7-91
7.5.2 Retry Operation
When the BERR and HALT signals are both asserted by an external device during a bus
cycle, the processor enters the retry sequence. A delayed retry, similar to the delayed bus
error signal described previously, can also occur, both for synchronous and asynchronous
cycles.
The processor terminates the bus cycle, places the control signals in their inactive state, and
does not begin another bus cycle until the HALT
signal is negated by external logic. After a
synchronization delay, the processor retries the previous cycle using the same access
information (address, function code, size, etc.) The BERR
signal should be negated before
S2 of the read cycle to ensure correct operation of the retried cycle. Figure 7-54 shows a
retry operation of an asynchronous cycle, and Figure 7-55 shows a retry operation of a
synchronous cycle.
The processor retries any read or write cycle of a read-modify-write operation separately;
RMC
remains asserted during the entire retry sequence.
On the initial access of a burst operation, a retry (indicated by the assertion of BERR
and
HALT
) causes the processor to retry the bus cycle and assert CBREQ again. Figure 7-56
shows a late retry operation that causes an initial burst operation to be repeated. However,
signaling a retry with simultaneous BERR
and HALT during the second, third, or fourth cycle
of a burst operation does not cause a retry operation, even if the requested operand is
misaligned. Assertion of BERR
and HALT during a subsequent cycle of a burst operation
causes independent BERR
and HALT operations. The external bus activity remains halted
until
HALT is negated and the processor acts as previously described for the bus error
during a burst operation.
Asserting BR
along with BERR and HALT provides a relinquish and retry operation. The
MC68030 does not relinquish the bus during a read-modify-write operation, except during
the first read cycle. Any device that requires the processor to give up the bus and retry a bus
cycle during a read-modify-write cycle must either assert
BERR and BR only (HALT must
not be included) or use the single wire arbitration method discussed in 7.7.4 Bus
Arbitration Control. The bus error handler software should examine the read-modify-write
bit in the special status word (refer to 8.2.1 Special Status Word (SSW)) and take the
appropriate action to resolve this type of fault when it occurs.
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