Motorola MC68030 User Manual

MOTOROLA MC68030 USER’S MANUAL xxv
TABLE OF CONTENTS
Paragraph
Number
Title
Page
Number
Section 1
Introduction
1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 MC68030 Extensions to the M68000 Family . . . . . . . . . . . . . . . . . . . 1-4
1.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Data Types and Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.5 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6 Virtual Memory and Virtual Machine Concepts . . . . . . . . . . . . . . . . . 1-12
1.6.1 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.6.2 Virtual Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.7 The Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.8 Pipelined Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.9 The Cache Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Section 2
Data Organization and Addressing Capabilities
2.1 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Organization of Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.1 Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2.2 Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 Organization of Data in Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.4.1 Data Register Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.4.2 Address Register Direct Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.4.3 Address Register Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.4.4 Address Register Indirect with Postincrement Mode. . . . . . . . . . . . 2-10
2.4.5 Address Register Indirect with Predecrement Mode . . . . . . . . . . . . 2-11
2.4.6 Address Register Indirect with Displacement Mode . . . . . . . . . . . . 2-12
2.4.7 Address Register Indirect with Index (8-Bit Displacement) Mode . . 2-12
2.4.8 Address Register Indirect with Index (Base Displacement) Mode. . 2-13
2.4.9 Memory Indirect Postindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.4.10 Memory Indirect Preindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.11 Program Counter Indirect with Displacement Mode . . . . . . . . . . . . 2-16
2.4.12 Program Counter Indirect with Index (8-Bit Displacement) Mode . . 2-16
2.4.13 Program Counter Indirect with Index (Base Displacement) Mode. . 2-17
2.4.14 Program Counter Memory Indirect Postindexed Mode . . . . . . . . . . 2-18
2.4.15 Program Counter Memory Indirect Preindexed Mode. . . . . . . . . . . 2-19
2.4.16 Absolute Short Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.17 Absolute Long Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.4.18 Immediate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.5 Effective Address Encoding Summary. . . . . . . . . . . . . . . . . . . . . . . . 2-22

Motorola MC68030 Specifications

General

Brand	Motorola
Model	MC68030
Category	Computer Hardware
Language	English

Summary

MOTOROLA MC68030 USER'S MANUAL

PREFACE

Provides an overview of the MC68030 User's Manual, its audience, and structure.

SECTION 1 INTRODUCTION

Introduces the MC68030 microprocessor, its features, and architecture.

1.1 FEATURES

Details the key features and capabilities of the MC68030 microprocessor.

1.4 DATA TYPES AND ADDRESSING MODES

1.7 THE MEMORY MANAGEMENT UNIT

Details the MMU's role in virtual memory and address translation.

1.9 THE CACHE MEMORIES

SECTION 2 DATA ORGANIZATION AND ADDRESSING CAPABILITIES

2.2 ORGANIZATION OF DATA IN REGISTERS

2.4 ADDRESSING MODES

Covers the various addressing modes for accessing operands.

SECTION 3 INSTRUCTION SET SUMMARY

3.2 INSTRUCTION SUMMARY

Categorizes and summarizes the MC68030 instructions.

SECTION 4 PROCESSING STATES

4.1 PRIVILEGE LEVELS

4.3 EXCEPTION PROCESSING

Details exception handling, vector table, and stack frames.

SECTION 5 SIGNAL DESCRIPTION

5.7 CACHE CONTROL SIGNALS

SECTION 6 ON-CHIP CACHE MEMORIES

6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

6.1.1 Instruction Cache

6.1.2 Data Cache

6.3 CACHE CONTROL

SECTION 7 BUS OPERATION

7.1 BUS TRANSFER SIGNALS

7.2 DATA TRANSFER MECHANISM

7.3 DATA TRANSFER CYCLES

Defines signals for data transfer and describes read, write, and RMW cycles.

7.3.1 Asynchronous Read Cycle

7.3.2 Asynchronous Write Cycle

7.3.7 Burst Operation Cycles

7.5 BUS EXCEPTION CONTROL CYCLES

Covers DSACKx, STERM, AVEC assertion requirements and MMU errors.

7.5.1 Bus Errors

7.7 BUS ARBITRATION

Describes bus arbitration protocol for single bus master operation.

7.8 RESET OPERATION

Describes system and processor reset mechanisms.