Motorola MC68020 User Manual

© MOTOROLA INC., 1992
MC68020
MC68EC020
MICROPROCESSORS
USER’S MANUAL
First Edition
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Motorola MC68020 Specifications

General

Brand	Motorola
Model	MC68020
Category	Computer Hardware
Language	English

Summary

SECTION 1 INTRODUCTION

1.1 FEATURES

1.2 PROGRAMMING MODEL

Description of the MC68020/EC020's internal registers and programming environment.

1.3 DATA TYPES AND ADDRESSING MODES OVERVIEW

Details on supported data types and memory addressing modes for programming.

1.4 INSTRUCTION SET OVERVIEW

1.6 PIPELINED ARCHITECTURE

1.7 CACHE MEMORY

Information on the on-chip instruction cache for performance improvement.

SECTION 2 PROCESSING STATES

2.1 PRIVILEGE LEVELS

Details on user and supervisor privilege levels and their impact on operation.

2.3 EXCEPTION PROCESSING

Description of how the processor handles exceptions, including vector tables and stack frames.

SECTION 4 ON-CHIP CACHE MEMORY

4.1 ON-CHIP CACHE ORGANIZATION AND OPERATION

Details on the direct-mapped cache organization and how it operates.

4.3 CACHE CONTROL

SECTION 5 BUS OPERATION

5.1 BUS TRANSFER SIGNALS

5.2 DATA TRANSFER MECHANISM

Explanation of how operands are transferred, including dynamic bus sizing.

5.3 DATA TRANSFER CYCLES

Description of bus cycles for data transfer, including read, write, and read-modify-write.

5.5 BUS EXCEPTION CONTROL CYCLES

5.7 BUS ARBITRATION

Description of the protocol for determining bus mastership between processor and external devices.

5.8 RESET OPERATION

SECTION 6 EXCEPTION PROCESSING

6.1 EXCEPTION PROCESSING SEQUENCE

Step-by-step description of how the processor enters and manages exception processing.

6.2 BUS FAULT RECOVERY

Details on recovering from bus errors and address errors using software.

6.4 EXCEPTION STACK FRAME FORMATS

SECTION 7 COPROCESSOR INTERFACE DESCRIPTION

7.1 INTRODUCTION

7.2 COPROCESSOR INSTRUCTION TYPES

Categorization of coprocessor instructions and their protocols.

7.3 COPROCESSOR INTERFACE REGISTER SET

7.4 COPROCESSOR RESPONSE PRIMITIVES

Detailed descriptions of the primitive instructions used for coprocessor status and service requests.

7.5 EXCEPTIONS

Overview of exceptions detected by the main processor or coprocessor.

SECTION 8 INSTRUCTION EXECUTION TIMING

8.1 TIMING ESTIMATION FACTORS

8.2 INSTRUCTION TIMING TABLES

Tables detailing clock periods for various instructions and addressing modes.

SECTION 10 ELECTRICAL CHARACTERISTICS

10.1 MAXIMUM RATINGS

10.2 THERMAL CONSIDERATIONS

10.3 AC ELECTRICAL CHARACTERISTICS