MOTOROLA M68020 USER’S MANUAL 7- 29
7.4.1 ScanPC
Several of the response primitives involve the scanPC, and many of them require the main
processor to use it while performing services requested. These paragraphs describe the
scanPC and its operation.
During the execution of a coprocessor instruction, the PC in the MC68020/EC020 contains
the address of the F-line operation word of that instruction. A second register, called the
scanPC, sequentially addresses the remaining words of the instruction.
If the main processor requires extension words to calculate an effective address or
destination address of a branch operation, it uses the scanPC to address these extension
words in the instruction stream. Also, if a coprocessor requests the transfer of extension
words, the scanPC addresses the extension words during the transfer. As the processor
references each word, it increments the scanPC to point to the next word in the instruction
stream. When an instruction has completed, the processor transfers the value in the
scanPC to the PC to address the operation word of the next instruction.
The value in the scanPC when the main processor reads the first response primitive after
beginning to execute an instruction depends on the instruction being executed. For a
cpGEN instruction, the scanPC points to the word following the coprocessor command
word. For the cpBcc instructions, the scanPC points to the word following the instruction
F-line operation word. For the cpScc, cpTRAPcc, and cpDBcc instructions, the scanPC
points to the word following the coprocessor condition specifier word.
If a coprocessor implementation uses optional instruction extension words with a general
or conditional instruction, the coprocessor must use these words consistently so that the
scanPC is updated accordingly during the instruction execution. Specifically, during the
execution of general category instructions, when the coprocessor terminates the
instruction protocol, the MC68020/EC020 assumes that the scanPC is pointing to the
operation word of the next instruction to be executed. During the execution of conditional
category instructions, when the coprocessor terminates the instruction protocol, the
MC68020/EC020 assumes that the scanPC is pointing to the word following the last of
any coprocessor-defined extension words in the instruction format.
7.4.2 Coprocessor Response Primitive General Format
The M68000 coprocessor response primitives are encoded in a 16-bit word that is
transferred to the main processor through the response CIR. Figure 7-22 shows the
format of the coprocessor response primitives.
15
FUNCTION
PARAMETERCA
Figure 7-22. Coprocessor Response Primitive Format
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