Motorola MC68020 User Manual

MOTOROLA M68020 USER’S MANUAL 7- 5
To improve the efficiency of operand transfers between memory and the coprocessor, a
coprocessor that requires a relatively high amount of bus bandwidth or has special bus
requirements can be implemented as a DMA coprocessor. The DMA coprocessor
provides all control, address, and data signals necessary to request and obtain the bus
and then performs DMA transfers using the bus. DMA coprocessors, however, must still
act as bus slaves when they require information or services of the main processor using
the M68000 coprocessor interface protocol.
7.1.4.2 PROCESSOR-COPROCESSOR INTERFACE. Figure 7-2 is a block diagram of
the signals involved in an asynchronous non-DMA M68000 coprocessor interface. Since
the CpID on signals A15–A13 of the address bus is used with other address signals to
select the coprocessor, the system designer can use several coprocessors of the same
type and assign a unique CpID to each one.
FC2–FC0
A19–A13
COPROCESSOR
DECODE
LOGIC
CS
COPROCESSOR
ASYNCHRONOUS
BUS
INTERFACE
LOGIC
AS
DS
R/W
A4–A1
D31–D0
DSACK1 / DSACK0
MAIN PROCESSOR
MC68020/EC020
FC2–FC0 = 111
A
19–A16 = 0010
A
15–A13 = xxx
A
4–A1 = rrrr
*Chip select logic may be integrated into the coprocessor.
Address lines not specified above are "0" during coprocessor access.
➧
➧
➧
➧
*
CPU SPACE CYCLE
C
OPROCESSOR ACCESS IN CPU SPACE
C
OPROCESSOR IDENTIFICATION
C
OPROCESSOR INFERFACE REGISTER SELECTOR
Figure 7-2. Asynchronous Non-DMA M68000
Coprocessor Interface Signal Usage
The MC68020/EC020 accesses the registers in the CIR set using standard asynchronous
bus cycles. Thus, the bus interface implemented by a coprocessor for its interface register
set must satisfy the MC68020/EC020 address, data, and control signal timing. The
MC68020/EC020 bus operation is described in detail in Section 5 Bus Operation.

Motorola MC68020 Specifications

General

Brand	Motorola
Model	MC68020
Category	Computer Hardware
Language	English