7- 42 M68020 USER’S MANUAL MOTOROLA
The D/A bit specifies whether the primitive transfers an address or data register. D/A = 0
indicates a data register, and D/A = 1 indicates an address register. The register field
contains the register number.
If DR = 0, the main processor writes the long-word operand in the specified register to the
operand CIR. If DR = 1, the main processor reads a long-word operand from the operand
CIR and transfers it to the specified data or address register.
7.4.14 Transfer Main Processor Control Register Primitive
The transfer main processor control register primitive transfers a long-word operand
between one of its control registers and the coprocessor. This primitive applies to general
and conditional category instructions. Figure 7-34 shows the format of the transfer main
processor control register primitive.
15
Figure 7-34. Transfer Main Processor Control Register Primitive Format
The transfer main processor control register primitive uses the CA, PC, and DR bits as
described in 7.4.2 Coprocessor Response Primitive General Format. If the
coprocessor issues this primitive with CA = 0 during a conditional category instruction, the
main processor initiates protocol violation exception processing.
When the main processor receives this primitive, it reads a control register select code
from the register select CIR. This code determines which main processor control register
is transferred. Table 7-5 lists the valid control register select codes. If the control register
select code is not valid, the MC68020/EC020 initiates protocol violation exception
processing (refer to 7.5.2.1 Protocol Violations).
Table 7-5. Main Processor Control
Register Select Codes
Select Code Control Register
$x000 SFC
$x001 DFC
$x002 CACR
$x800 USP
$x801 VBR
$x802 CAAR
$x803 MSP
$x804 ISP
All other codes cause a protocol violation exception.
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