5- 76 M68020 USER’S MANUAL MOTOROLA
An example of MC68EC020 bus arbitration to a DMA device that supports three-wire bus
arbitration is described in Appendix A Interfacing an MC68EC020 to a DMA Device
That Supports a Three-Wire Bus Arbitration Protocol.
B
B
BGAC
BUS MASTER
G
Figure 5-50. Interface for Three-Wire to Two-Wire Bus Arbitration
5.8 RESET OPERATION
RESET is a bidirectional signal with which an external device resets the system or the
processor resets external devices. When power is applied to the system, external circuitry
should assert RESET for a minimum of 520 clocks after V
CC
and clock timing have
stabilized and are within specification limits. Figure 5-51 is a timing diagram of the power-
up reset operation, showing the relationships between RESET, V
CC
, and bus signals. The
clock signal is required to be stable by the time V
CC
reaches the minimum operating
specification. During the reset period, the entire bus three-states (except for non-three-
statable signals, which are driven to their inactive state). Once RESET negates, all control
signals are negated, the data bus is in read mode, and the address bus is driven. After
this, the first bus cycle for reset exception processing begins.
The external RESET signal resets the processor and the entire system. Except for the
initial reset, RESET should be asserted for at least 520 clock periods to ensure that the
processor resets. Asserting RESET for 10 clock periods is sufficient for resetting the
processor logic; the additional clock periods prevent a RESET instruction from overlapping
the external RESET signal.
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