Motorola MC68020 User Manual

5- 64 M68020 USER’S MANUAL MOTOROLA
1) ASSERT BG
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
1) NEGATE BG AND WAIT FOR BGACK TO
BE NEGATED
RE-ARBITRATE OR RESUME
PROCESSOR OPERATION
REQUEST THE BUS
1) ASSERT BR
REQUESTING DEVICE
PROCESSOR
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2
) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
3
) NEXT BUS MASTER ASSERTS BGACK
T
O BECOME NEW MASTER
4
) BUS MASTER NEGATES BR
OPERATE AS BUS MASTER
RELEASE BUS MASTERSHIP
1) PERFORM DATA TRANSFERS
(READ AND WRITE CYCLES)
1) NEGATE BGACK
Figure 5-42. MC68020 Bus Arbitration Flowchart for Single Request
The timing diagram (see Figure 5-43) shows that BR is negated at the time that BGACK is
asserted. This type of operation applies to a system consisting of the processor and one
device capable of bus mastership. In a system having a number of devices capable of bus
mastership, the BR line from each device can be wire-ORed to the processor. In such a
system, more than one bus request can be asserted simultaneously.
The timing diagram in Figure 5-43 shows that BG is negated a few clock cycles after the
transition of BGACK. However, if bus requests are still pending after the negation of BG,
the processor asserts another BG within a few clock cycles after it was negated. This
additional assertion of BG allows external arbitration circuitry to select the next bus master
before the current bus master has finished with the bus. The following paragraphs provide
additional information about the three steps in the arbitration process.
Bus arbitration requests are recognized during normal processing, RESET assertion,
HALT assertion, and when the processor has halted due to a double bus fault.

Motorola MC68020 Specifications

General

Brand	Motorola
Model	MC68020
Category	Computer Hardware
Language	English