7- 28 M68020 USER’S MANUAL MOTOROLA
7.3.9 Register Select CIR
When the coprocessor requests the transfer of one or more main processor registers or a
group of coprocessor registers, the main processor reads the 16-bit register select CIR to
identify the number or type of registers to be transferred. The offset from the base address
of the CIR set for the register select CIR is $14. The format of this register depends on the
primitive that is currently using it (refer to 7.4 Coprocessor Response Primitives).
7.3.10 Instruction Address CIR
When the coprocessor requests the address of the instruction it is currently executing, the
main processor transfers this address to the 32-bit instruction address CIR. Any transfer of
the scanPC is also performed through the instruction address CIR (refer to 7.4.17
Transfer Status Register and ScanPC Primitive). The offset from the base address of
the CIR set for the instruction address CIR is $18.
7.3.11 Operand Address CIR
When a coprocessor requests an operand address transfer between the main processor
and the coprocessor, the address is transferred through the 32-bit operand address CIR.
The offset from the base address of the CIR set for the operand address CIR is $1C.
7.4 COPROCESSOR RESPONSE PRIMITIVES
The response primitives are primitive instructions that the coprocessor issues to the main
processor during the execution of a coprocessor instruction. The coprocessor uses
response primitives to communicate status information and service requests to the main
processor. In response to an instruction command word written to the command CIR or a
condition selector in the condition CIR, the coprocessor returns a response primitive in the
response CIR. Within the general and conditional instruction categories, individual
instructions are distinguished by the operation of the coprocessor hardware and by
services specified by coprocessor response primitives and provided by the main
processor.
Subsequent paragraphs, beginning with 7.4.2 Coprocessor Response Primitive
General Format, consist of detailed descriptions of the M68000 coprocessor response
primitives supported by the MC68020/EC020. Any response primitive that the
MC68020/EC020 does not recognize causes it to initiate protocol violation exception
processing (refer to 7.5.2.1 Protocol Violations). This processing of undefined primitives
supports emulation of extensions to the M68000 coprocessor response primitive set by
the protocol violation exception handler. Exception processing related to the coprocessor
interface is discussed in 7.5 Exceptions.
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