8- 30 M68020 USER’S MANUAL MOTOROLA
8.2.8 Arithmetic/Logical Instructions
The arithmetic/logical instructions table indicates the number of clock periods needed for
the processor to perform the specified arithmetic/logical operation using the specified
addressing mode. It also includes, in worst case, the amount of time needed to prefetch
the next instruction. Footnotes specify when to add either fetch address or fetch
immediate effective address time. This sum gives the total effective execution time for the
operation using the specified addressing mode. The total number of clock cycles is
outside the parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Instruction Best Case Cache Case Worst Case
* ADD EA,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* ADDA EA,An 0(0/0/0) 2(0/0/0) 3(0/1/0)
* ADD Dn,EA 3(0/0/1) 4(0/0/1) 6(0/1/1)
* AND EA,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* AND Dn,EA 3(0/0/1) 4(0/0/1) 6(0/1/1)
* EOR Dn,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* EOR Dn,Mem 3(0/0/1) 4(0/0/1) 6(0/1/1)
* OR EA,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* OR Dn,EA 3(0/0/1) 4(0/0/1) 6(0/1/1)
* SUB EA,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* SUBA EA,An 0(0/0/0) 2(0/0/0) 3(0/1/0)
* SUB Dn,EA 3(0/0/1) 4(0/0/1) 6(0/1/1)
* CMP EA,Dn 0(0/0/0) 2(0/0/0) 3(0/1/0)
* CMPA EA,An 1(0/0/0) 4(0/0/0) 4(0/1/0)
** CMP2 EA,Rn 16(1/0/0) 18(1/0/0) 18(1/1/0)
* MUL.W EA,Dn 25(0/0/0) 27(0/0/0) 28(0/1/0)
** MUL.L EA,Dn 41(0/0/0) 43(0/0/0) 44(0/1/0)
* DIVU.W EA,Dn 42(0/0/0) 44(0/0/0) 44(0/1/0)
** DIVU.L EA,Dn 76(0/0/0) 78(0/0/0) 79(0/1/0)
* DIVS.W EA,Dn 54(0/0/0) 56(0/0/0) 57(0/1/0)
** DIVS.L EA,Dn 88(0/0/0) 90(0/0/0) 91(0/1/0)
*Add Fetch Effective Address Time
** Add Fetch Immediate Address Time
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