8- 36 M68020 USER’S MANUAL MOTOROLA
8.2.14 Bit Field Manipulation Instructions
The bit field manipulation instructions table indicates the number of clock periods needed
for the processor to perform the specified bit field operation using the given addressing
mode. Footnotes indicate when it is necessary to add another table entry to calculate the
total effective execution time for the instruction. The total number of clock cycles is outside
the parentheses; the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Instruction Best Case Cache Case Worst Case
BFTST Dn 3(0/0/0) 6(0/0/0) 7(0/1/0)
‡ BFTST Mem (< 5 Bytes) 11(1/0/0) 11(1/0/0) 12(1/1/0)
‡ BFTST Mem (5 Bytes) 15(2/0/0) 15(2/0/0) 16(2/1/0)
BFCHG Dn 9(0/0/0) 12(0/0/0) 12(0/1/0)
‡ BFCHG Mem (< 5 Bytes) 16(1/0/1) 16(1/0/1) 16(1/1/1)
‡ BFCHG Mem (5 Bytes) 24(2/0/2) 24(2/0/2) 24(2/1/2)
BFCLR Dn 9(0/0/0) 12(0/0/0) 12(0/1/0)
‡ BFCLR Mem (< 5 Bytes) 16(1/0/1) 16(1/0/1) 16(1/1/1)
‡ BFCLR Mem (5 Bytes) 24(2/0/2) 24(2/0/2) 24(2/1/2)
BFSET Dn 9(0/0/0) 12(0/0/0) 12(0/1/0)
‡ BFSET Mem (< 5 Bytes) 16(1/0/1) 16(1/0/1) 16(1/1/1)
‡ BFSET Mem (5 Bytes) 24(2/0/2) 24(2/0/2) 24(2/1/2)
BFEXTS Dn 5(0/0/0) 8(0/0/0) 8(0/1/0)
‡ BFEXTS Mem (< 5 Bytes) 13(1/0/0) 13(1/0/0) 13(1/1/0)
‡ BFEXTS Mem (5 Bytes) 18(2/0/0) 18(2/0/0) 18(2/1/0)
BFEXTU Dn 5(0/0/0) 8(0/0/0) 8(0/1/0)
‡ BFEXTU Mem (< 5 Bytes) 13(1/0/0) 13(1/0/0) 13(1/1/0)
‡ BFEXTU Mem (5 Bytes) 18(2/0/0) 18(2/0/0) 18(2/1/0)
BFINS Dn 7(0/0/0) 10(0/0/0) 10(0/1/0)
‡ BFINS Mem (< 5 Bytes) 14(1/0/1) 14(1/0/1) 15(1/1/1)
‡ BFINS Mem (5 Bytes) 20(2/0/2) 20(2/0/2) 21(2/1/2)
BFFFO Dn 15(0/0/0) 18(0/0/0) 18(0/1/0)
‡ BFFFO Mem (< 5 Bytes) 24(1/0/0) 24(1/0/0) 24(1/1/0)
‡ BFFFO Mem (5 Bytes) 32(2/0/0) 32(2/0/0) 32(2/1/0)
‡Add Calculate Immediate Address Time
NOTE: A bit field of 32 bits may span five bytes that require two operand cycles to access or may span four bytes that
require only one operand cycle to access.
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