MOTOROLA M68020 USER’S MANUAL 8- 9
8.2 INSTRUCTION TIMING TABLES
The instruction times given in the following illustration include the following assumptions
about the MC68020/EC020 system:
1. All operands are long-word aligned as is the stack,
2. The data bus is 32 bits, and
3. Memory access occurs with no wait states (three-cycle read/write).
There are three values given for each instruction and addressing mode:
1. The best case (BC), which reflects the time (in clocks) when the instruction is in the
cache and benefits from maximum overlap due to other instructions,
2. The cache-only case (CC) when the instruction is in the cache but has no overlap,
and
3. The worst case (WC) when the instruction is not in the cache or the cache is
disabled and there is no instruction overlap.
The only instances for which the size of the operand has any effect are the instructions
with immediate operands. Unless specified otherwise, immediate byte and word operands
have identical execution times.
Within each set or column of instruction timings are four sets of numbers, three of which
are enclosed in parentheses. The bolded outer number is the total number of clocks for
the instruction. The first number inside the parentheses is the number of operand read
cycles performed by the instruction. The second value inside parentheses is the number
of instruction accesses performed by the instruction, including all prefetches to keep the
instruction pipe filled. The third value within parentheses is the number of write cycles
performed by the instruction. One example from the instruction timing table is:
NUMBER OF READ CYCLE
NUMBER OF INSTRUCTION ACCESS CYCLE
NUMBER OF WRITE CYCLE
The total number of bus-activity clocks for the previous example is derived in the following
way:
(2 Reads
*
3 Clocks/Read) + (3 Instruction Accesses
*
3 Clocks/Access)
+ (0 Writes
*
3 Clocks/Write) = 15 Clocks of Bus Activity
24 Total Clocks – 15 Clocks (Bus Activity) = 9 Internal Clocks
The example used here was taken from a worst-case fetch effective address time. The
addressing mode was ([d
32
,B],I,d
32
). The same addressing mode under the best-case
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