MOTOROLA M68020 USER’S MANUAL 9- 3
The major concern of a system designer is to design a CS interface that meets the AC
electrical specifications for both the MC68020/EC020 (MPU) and the MC68881/MC68882
(FPCP) without adding unnecessary wait states to FPCP accesses. The following
maximum specifications (relative to CLK low) meet these objectives:
t
CLK
low to AS low ≤ (MPU Spec 1 – MPU Spec 47A – FPCP Spec 19) (9-1)
t
CLK
low to CS low ≤ (MPU Spec 1 – MPU Spec 47A – FPCP Spec 19) (9-2)
Even though requirement (9-1) is not met under worst-case conditions, if the MPU
AS is
loaded within specifications and the
AS input to the FPCP is unbuffered, the requirement
is met under typical conditions. Designing the
CS generation circuit to meet requirement
(9-2) provides the highest probability that accesses to the FPCP occur without
unnecessary wait states. A PAL 16L8 (see Figure 9-2) with a maximum propagation delay
of 10 ns, programmed according to the equations in Figure 9-3, can be used to generate
CS. For a 25-MHz system, t
CLK
low to CS low is less than or equal to 10 ns when this
design is used. Should worst-case conditions cause t
CLK
low to AS low to exceed
requirement (1), one wait state is inserted in the access to the FPCP; no other adverse
effects occur. Figure 9-4 shows the bus cycle timing for this interface. Refer to
MC68881UM/AD,
MC68881/MC68882 Floating-Point Coprocessor User's Manual
, for
FPCP specifications.
The circuit that generates
CS must meet another requirement. When a nonfloating-point
access immediately follows a floating-point access,
CS (for the floating-point access) must
be negated before
AS and DS (for the subsequent access) are asserted. The PAL circuit
previously described also meets this requirement.
10 ns
Figure 9-2. Chip Select Generation PAL
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