Motorola MC68020 User Manual

MOTOROLA M68020 USER’S MANUAL 8- 19
8.2.5 Jump Effective Address
The jump effective address table indicates the number of clock periods needed for the
processor to calculate the specified effective address. Fetch time is only included for the
first level of indirection on memory indirect addressing modes. The total number of clock
cycles is outside the parentheses; the number or read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). These cycles are included in the total clock cycle
number.
Address Mode Best Case Cache Case Worst Case
(An) 0(0/0/0) 2(0/0/0) 2(0/0/0)
(d
16
,An) 1(0/0/0) 4(0/0/0) 4(0/0/0)
(xxx).W 0(0/0/0) 2(0/0/0) 2(0/0/0)
(xxx).L 0(0/0/0) 2(0/0/0) 2(0/0/0)
(d
8
,An,Xn) or (d
8
,PC,Xn) 3(0/0/0) 6(0/0/0) 6(0/0/0)
(d
16
,An,Xn) or (d
16
,PC,Xn) 3(0/0/0) 6(0/0/0) 6(0/0/0)
(B) 3(0/0/0) 6(0/0/0) 6(0/0/0)
(B,d
16
) 5(0/0/0) 8(0/0/0) 8(0/1/0)
(B,d
32
) 9(0/0/0) 12(0/0/0) 12(0/1/0)
([B],I) 8(1/0/0) 11(1/0/0) 11(1/1/0)
([B],I,d
16
) 10(1/0/0) 13(1/0/0) 14(1/1/0)
([B],I,d
32
) 10(1/0/0) 13(1/0/0) 14(1/1/0)
([d
16
,B],I) 10(1/0/0) 13(1/0/0) 14(1/1/0)
([d
16
,B],I,d
16
) 12(1/0/0) 15(1/0/0) 17(1/1/0)
([d
16
,B],I,d
32
) 12(1/0/0) 15(1/0/0) 17(1/1/0)
([d
32
,B],I) 14(1/0/0) 17(1/0/0) 19(1/2/0)
([d
32
,B],I,d
16
) 16(1/0/0) 19(1/0/0) 21(1/2/0)
([d
32
,B],I,d
32
) 16(1/0/0) 19(1/0/0) 23(1/2/0)
B = Base address; 0, An, PC, Xn, An + Xn, PC + Xn. Form does not affect timing.
I = Index; 0, Xn
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.

Motorola MC68020 Specifications

General

Brand	Motorola
Model	MC68020
Category	Computer Hardware
Language	English