Motorola MC68020 User Manual

MOTOROLA M68020 USER’S MANUAL 5- 77
ISP
R
EAD
S
TART
S
ALL CONTROL SIGNALS
NEGATED, DATA BUS IN
READ MODE, ADDRESS
BUS DRIVEN
ENTIRE BUS
THREE-
STATED
BUS STATE UNKNOWN
t
≥
520 CLOCKS
t < 4 CLOCKS
4 CLOCKS
CLK
+5 V
V
CC
BUS
CYCLE
S
RESET
Figure 5-51. Initial Reset Operation Timing
Resetting the processor causes any bus cycle in progress to terminate as if
DSACK1/DSACK0 or BERR had been asserted. In addition, the processor initializes
registers appropriately for a reset exception. Exception processing for a reset operation is
described in Section 6 Exception Processing.
When a RESET instruction is executed, the processor drives the RESET signal for 512
clock cycles. In this case, the processor resets the external devices of the system, and the
internal registers of the processor are unaffected. The external devices connected to the
RESET signal are reset at the completion of the RESET instruction. An external RESET
signal that is asserted to the processor during execution of a RESET instruction must
extend beyond the reset period of the instruction by at least eight clock cycles to reset the
processor. Figure 5-52 shows the timing information for the RESET instruction.

Motorola MC68020 Specifications

General

Brand	Motorola
Model	MC68020
Category	Computer Hardware
Language	English