MOTOROLA M68020 USER’S MANUAL 4- 3
4.2 CACHE RESET
During processor reset, the cache is cleared by resetting all of the valid bits. The E and F
bits in the CACR are also cleared.
4.3 CACHE CONTROL
Only the MC68020/EC020 cache control circuitry can directly access the cache array, but
a supervisor program can set bits in the CACR to exercise control over cache operations.
The supervisor level also has access to the CAAR, which contains the address for a
cache entry to be cleared.
System hardware can assert the
CDIS signal to disable the cache. The assertion of CDIS
disables the cache, regardless of the state of the E-bit in the CACR. CDIS is primarily
intended for use by in-circuit emulators.
4.3.1 Cache Control Register (CACR)
The CACR, shown in Figure 4-2, is a 32-bit register than can be written or read by the
MOVEC instruction or indirectly modified by a reset. Four of the bits (3–0) control the
instruction cache. Bits 31–4 are reserved for Motorola definition. They are read as zeros
and are ignored when written. For future compatibility, writes should not set these bits.
0
E
0
Figure 4-2. Cache Control Register
C—Clear Cache
The C-bit is set to clear all entries in the instruction cache. Operating systems and other
software set this bit to clear instructions from the cache prior to a context switch. The
processor clears all valid bits in the instruction cache when a MOVEC instruction sets
the C-bit. The C-bit is always read as a zero.
CE—Clear Entry In Cache
The CE bit is set to clear an entry in the instruction cache. The index field of the CAAR
(see Figure 4-3), corresponding to the index and long-word select portion of an address,
specifies the entry to be cleared. The processor clears only the specified long word by
clearing the valid bit for the entry when a MOVEC instruction sets the CE bit, regardless
of the states of the E and F bits. The CE bit is always read as a zero.
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