9- 10 M68020 USER’S MANUAL MOTOROLA
Table 9-2. V
CC
and GND Pin Assignments—
MC68EC020 PPGA (RP Suffix)
Pin Group V
CC
GND
Address Bus B7, C7 A1, A7, C8, D13
Data Bus K12, M9, N9 J13, L8, M1, M8
Internal Logic D1, D2, E12, E13 F11, F12, J1, J2
Clock — B1
Table 9-3. V
CC
and GND Pin Assignments—
MC68EC020 PQFP (FG Suffix)
Pin Group V
CC
GND
Address Bus 90 72, 89, 100
Data Bus 44, 57 26, 43, 58, 59
Internal Logic 7, 8, 70, 71 3, 20, 21, 68, 69
Clock — 4
9.4 CLOCK DRIVER
The MC68020/EC020 is designed to sustain high performance while using low-cost
memory subsystems. The MC68020/EC020 requires a stable clock source that is free of
ringing and ground bounce, has sufficient rise and fall times, and meets the minimum and
maximum high and low cycle times. The individual system may require additional clocks
for peripherals with a minimum amount of clock skew. Two possible clock solutions are
provided with the MC88916 and MC74F803. Many other clock solutions can be used.
Some crystal clock drivers are capable of driving the MC68020/EC020 directly. For slower
speed designs, a simple 74F74 flip-flop meets the clocking needs of the MC68020/EC020.
Coupled with the MC88916 or MC74F803 clock generation and distribution circuit, the
MC68020/EC020 provides simple interface to lower speed memory subsystems. The
MC88916 (see Figure 9-7) and MC74F803 (see Figure 9-8) generate the clock signals
required to minimize the skew between different clocks to multiple devices such as
coprocessors, synchronous state machines, DRAM controllers, and memory subsystems.
The MC88916 clock driver can be used in doubling and synchronizing a low-frequency
clock source. The MC74F803 will provide a controlled skew output for clocking other
peripherals.
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