Motorola MC68020 - Fetch Effective Address

MOTOROLA M68020 USER’S MANUAL 8- 13
8.2.1 Fetch Effective Address
The fetch effective address table indicates the number of clock periods needed for the
processor to calculate and fetch the specified effective address. The total number of clock
cycles is outside the parentheses; the number of read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). These cycles are included in the total clock cycle
number.
Address Mode Best Case Cache Case Worst Case
Dn 0(0/0/0) 0(0/0/0) 0(0/0/0)
An 0(0/0/0) 0(0/0/0) 0(0/0/0)
(An) 3(1/0/0) 4(1/0/0) 4(1/0/0)
(An)+ 4(1/0/0) 4(1/0/0) 4(1/0/0)
–(An) 3(1/0/0) 5(1/0/0) 5(1/0/0)
(d
16
,An) of (d
16
,PC) 3(1/0/0) 5(1/0/0) 6(1/1/0)
(xxx).W 3(1/0/0) 4(1/0/0) 6(1/1/0)
(xxx).L 3(1/0/0) 4(1/0/0) 7(1/1/0)
#<data>.B 0(0/0/0) 2(0/0/0) 3(0/1/0)
#<data>.W 0(0/0/0) 2(0/0/0) 3(0/1/0)
#<data>.L 0(0/0/0) 4(0/0/0) 5(0/1/0)
(d
8
,An,Xn) or (d
8
,PC,Xn) 4(1/0/0) 7(1/0/0) 8(1/1/0)
(d
16
,An,Xn) or (d
16
,PC,Xn) 4(1/0/0) 7(1/0/0) 9(1/1/0)
(B) 4(1/0/0) 7(1/0/0) 9(1/1/0)
(d
16
,B) 6(1/0/0) 9(1/0/0) 12(1/1/0)
(d
32
,B) 10(1/0/0) 13(1/0/0) 16(1/2/0)
([B],I) 9(2/0/0) 12(2/0/0) 13(2/1/0)
([B],I,d
16
) 11(2/0/0) 14(2/0/0) 16(2/1/0)
([B],I,d
32
) 11(2/0/0) 14(2/0/0) 17(2/2/0)
([d
16
,B],I) 11(2/0/0) 14(2/0/0) 16(2/1/0)
([d
16
,B],I,d
16
) 13(2/0/0) 16(2/0/0) 19(2/2/0)
([d
16
,B],I,d
32
) 13(2/0/0) 16(2/0/0) 20(2/2/0)
([d
32
,B],I) 15(2/0/0) 18(2/0/0) 20(2/2/0)
([d
32
,B],I,d
16
) 17(2/0/0) 20(2/0/0) 22(2/2/0)
([d
32
,B],I,d
32
) 17(2/0/0) 20(2/0/0) 24(2/3/0)
B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing.
I = Index; 0, Xn
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.