8- 12 M68020 USER’S MANUAL MOTOROLA
Comparing Tables 8-2 and 8-3 demonstrates that calculation of instruction timing cannot
be a simple lookup of only BC or only WC timings. Even when the assumptions are known
and fixed, as in the four examples summarized in Table 8-3, the microprocessor can
sometimes achieve best-case timings under worst-case assumptions.
Looking across the four examples in Table 8-3 for an individual instruction, it is difficult to
predict which timing table entry is used, since the influence of instruction overlap may or
may not improve the BC, WC, or CC timings. When looking at the observed instruction
timings for one example, it is also difficult to determine which combination of BC/CC/WC
timing is required. Just how the instruction stream will fit and run with the cache enabled,
how instructions are positioned in memory, and the degree of instruction overlap are
factors that are impossible to account for in all combinations of the timing tables.
Although the timing tables cannot accurately predict the instruction timing that would be
observed when executing an instruction stream on the MC68020/EC020, the tables can
be used to calculate best-case and worst-case bounds for instruction timing. Absolute
instruction timing must be measured by using the microprocessor itself to execute the
target instruction stream.
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