Motorola MC68020 User Manual

8- 6 M68020 USER’S MANUAL MOTOROLA
Example 2
Using the same instruction stream, the second example demonstrates the different effects
of instruction execution overlap on instruction timing when the same instructions are
positioned slightly differently in 32-bit memory:
Address n MOVE #1 ADD #2
n + 4 MOVE #3 ADD #4
n + 8 ••• •••
The assumptions for example 2 (see Figure 8-4) are:
1. The data bus is 32 bits,
2. The first instruction is prefetched from an even-word address,
3. Memory access occurs with no wait states, and
4. The cache is disabled.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLOCK
BUS
ACTIVIT
Y
PREFETCH
WRITE
READ
PREFETCH
WRITE
PREFETCH
BYTES n + 1
2
BUS
C
ONTROLLE
R
WRITE TO (A1)+
PREFETCH
BYTES n + 8
WRITE TO –(A2)
READ FROM (A1)
IDLE
PERFORM
MOVE #1
PERFORM
ADD #2
CALCULATE
S
OURCE E
A
MOVE #3
CALCULATE
D
ESTINATIO
N
EA
MOVE #3
PERFORM
MOVE #3
MOVE.L D4,(A1)+
MOVE.L (A1),–(A2)
ADD.L D5,D6
SEQUENCER
INSTRUCTION
E
XECUTION TIM
E
(4)
(3)
(3)
CLOCK
COUNTE
R
LEGEND:
1) MOVE.L D4,(A1)+
2) ADD.L D4,D5
3) MOVE.L (A1),–(A2)
4) ADD.L D5,D6
IDLE
NEXT
I
NSTRUCTIO
N
ADD.L D4,D5
(6)
PERFORM
ADD #4
IDLE
Figure 8-4. Processor Activity for Example 2
Although the total execution time of the instruction segment does not change in this
example, the individual instruction times are significantly different. This example
demonstrates that the effects of overlap are not only instruction-sequence dependent but
are also dependent upon the alignment of the instruction stream in memory.

Motorola MC68020 Specifications

General

Brand	Motorola
Model	MC68020
Category	Computer Hardware
Language	English