5- 60 M68020 USER’S MANUAL MOTOROLA
5.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the MC68020/EC020 halts external
bus activity at the next bus cycle boundary. HALT by itself does not terminate a bus cycle.
Negating and reasserting HALT in accordance with the correct timing requirements
provides a single-step (bus cycle to bus cycle) operation. The HALT signal affects external
bus cycles only; thus, a program that resides in the instruction cache and does not require
use of the external bus may continue executing unaffected by HALT.
The single-cycle mode allows the user to proceed through (and debug) external processor
operations, one bus cycle at a time. Figure 5-41 shows the timing requirements for a
single-cycle operation. Since the occurrence of a bus error while HALT is asserted causes
a retry operation, the user must anticipate retry cycles while debugging in the single-cycle
mode. The single-step operation and the software trace capability allow the system
debugger to trace single bus cycles, single instructions, or changes in program flow.
These processor capabilities, along with a software debugging package, give complete
debugging flexibility.
When the processor completes a bus cycle with the HALT signal asserted, the data bus is
placed in the high-impedance state, and the bus control signals (AS, DS , and, for the
MC68020 only, ECS and OCS) are negated (not placed in the high-impedance state);
A31–A0 for the MC68020 or A23–A0 for the MC68EC020, FC2–FC0, SIZ1, SIZ0, and
R/W remain in the same state. The halt operation has no effect on bus arbitration (refer to
5.7 Bus Arbitration). When bus arbitration occurs while the MC68020/EC020 is halted,
the address and control signals (A31–A0, FC2–FC0, SIZ1, SIZ0, R/W, AS, DS, and, for
the MC68020 only, ECS and OCS) are also placed in the high-impedance state. Once bus
mastership is returned to the MC68020/EC020, if HALT is still asserted, A31–A0 for the
MC68020 or A23–A0 for the MC68EC020, FC2–FC0, SIZ1, SIZ0, and R/W are again
driven to their previous states. The MC68020/EC020 does not service interrupt requests
while it is halted (although the MC68020 may assert the IPEND signal as appropriate).
5.5.4 Double Bus Fault
When a bus error or an address error occurs during the exception processing sequence
for a previous bus error, a previous address error, or a reset exception, a double bus fault
occurs. For example, the processor attempts to stack several words containing
information about the state of the machine while processing a bus error exception. If a bus
error exception occurs during the stacking operation, the second error is considered a
double bus fault. When a double bus fault occurs, the processor halts and asserts HALT.
Only an external reset operation can restart a halted processor. However, bus arbitration
can still occur (refer to 5.7 Bus Arbitration).
A second bus error or address error that occurs after exception processing has completed
(during the execution of the exception handler routine or later) does not cause a double
bus fault. A bus cycle that is retried does not constitute a bus error or contribute to a
double bus fault. The processor continues to retry the same bus cycle as long as the
external hardware requests it.
To Next Page
Loading...
Need help?
General
