Motorola MC68020 - Calculate Effective Address

8- 16 M68020 USER’S MANUAL MOTOROLA
8.2.3 Calculate Effective Address
The calculate immediate effective address table indicates the number of clock periods
needed for the processor to calculate the specified effective address. Fetch time is only
included for the first level of indirection on memory indirect addressing modes. The total
number of clock cycles is outside the parentheses; the number of read, prefetch, and write
cycles is given inside the parentheses as (r/p/w). These cycles are included in the total
clock cycle number.
Address Mode Best Case Cache Case Worst Case
Dn 0(0/0/0) 0(0/0/0) 0(0/0/0)
An 0(0/0/0) 0(0/0/0) 0(0/0/0)
(An) 2(0/0/0) 2(0/0/0) 2(0/0/0)
(An)+ 2(0/0/0) 2(0/0/0) 2(0/0/0)
–(An) 2(0/0/0) 2(0/0/0) 2(0/0/0)
(d
16
,An) or (d
16
,PC) 2(0/0/0) 2(0/0/0) 3(0/1/0)
<data>.W 2(0/0/0) 2(0/0/0) 3(0/1/0)
<data>.L 1(0/0/0) 4(0/0/0) 5(0/1/0)
(d
8
,An,Xn) or (d
8
,PC,Xn) 1(0/0/0) 4(0/0/0) 5(0/1/0)
(d
16
,An,Xn) or (d
16
,PC,Xn) 3(0/0/0) 6(0/0/0) 7(0/1/0)
(B) 3(0/0/0) 6(0/0/0) 7(0/1/0)
(d
16
,B) 5(0/0/0) 8(0/0/0) 10(0/1/0)
(d
32
,B) 9(0/0/0) 12(0/0/0) 15(0/2/0)
([B],I) 8(1/0/0) 11(1/0/0) 12(1/1/0)
([B],I,d
16
) 10(1/0/0) 13(1/0/0) 15(1/1/0)
([B],I,d
32
) 10(1/0/0) 13(1/0/0) 16(1/2/0)
([d
16
,B],I) 10(1/0/0) 13(1/0/0) 15(1/1/0)
([d
16
,B],I,d
16
) 12(1/0/0) 15(1/0/0) 18(1/2/0)
([d
16
,B],I,d
32
) 12(1/0/0) 15(1/0/0) 19(1/2/0)
([d
32
,B],I) 14(1/0/0) 17(1/0/0) 19(1/2/0)
([d
32
,B],I,d
16
) 16(1/0/0) 19(1/0/0) 21(1/2/0)
([d
32
,B],I,d
32
) 16(1/0/0) 19(1/0/0) 24(1/3/0)
B = Base address; 0, An, PC, Xn, An + Xn. Form does not affect timing.
I = Index; 0, Xn
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.