Motorola MC68020 - MC68 EC020 Bus Arbitration Operation Timing-Bus Inactive

MOTOROLA M68020 USER’S MANUAL 5- 75
A23–A0
FC2–FC0
AS
DS
DSACK1
CLK
S4
S0
SIZ1–SIZ0
R/W
DSACK0
BG
BR
D31–D0
PROCESSOR
PROCESSOR
ALTERNATE MASTER
BUS INACTIVE
(ARBITRATION PERMITTED
WHILE THE PROCESSOR IS
INACTIVE OR HALTED)
Figure 5-49. MC68EC020 Bus Arbitration Operation Timing—Bus Inactive
The existing three-wire arbitration design (BR, BG, and BGACK) of some peripherals can
be converted to the MC68EC020 two-wire arbitration with the addition of an AND gate.
Figure 5-50 shows the combination of BR and BGACK for a three-wire arbitration system
to BR of the MC68EC020 or BR and BG from an MC68EC020 to BG for a three-wire
arbitration system. The speed of the AND gate must be faster than the time between the
assertion of BGACK and the negation of BR by the alternate bus master. Figure 5-50
assumes the alternate bus master does not assume bus mastership until the MC68EC020
AS is negated and MC68EC020 BG is asserted.