7- 14 M68020 USER’S MANUAL MOTOROLA
return a response primitive to request services necessary to evaluate the condition. If the
coprocessor returns the false condition indicator, the main processor executes the next
instruction in the instruction stream. If the coprocessor returns the true condition indicator,
the main processor adds the displacement to the MC68020/EC020 scanPC (refer to 7.4.1
ScanPC) to determine the address of the next instruction for the main processor to
execute. The scanPC must be pointing to the location of the first word of the displacement
in the instruction stream when the address is calculated. The displacement is a twos-
complement integer that can be either a 16-bit word or a 32-bit long word. The main
processor sign-extends the 16-bit displacement to a long-word value for the destination
address calculation.
7.2.2.2 SET ON COPROCESSOR CONDITION INSTRUCTION. The set on coprocessor
condition instruction sets or resets a flag (a data alterable byte) according to a condition
evaluated by the coprocessor. The operation of this instruction type is similar to the
operation of the Scc instruction in the M68000 family instruction set. Although the Scc
instruction and the cpScc instruction do not explicitly cause a change of program flow,
they are often used to set flags that control program flow.
7.2.2.2.1 Format. Figure 7-11 shows the format of the set on coprocessor condition
instruction, denoted by the cpScc mnemonic.
15
CpID
0
FFECTIVE ADDRES
PTIONAL COPROCESSOR-DEFINED EXTENSION WORD
PTIONAL EFFECTIVE ADDRESS EXTENSION WORDS (0–5 WORDS
ONDITION SELECTOR
ESERVE
Figure 7-11. Set on Coprocessor Condition Instruction Format (cpScc)
The first word of the cpScc instruction, the F-line operation word, contains the CpID field in
bits 11–9 and 001 in bits 8–6 to identify the cpScc instruction. Bits 5–0 of the F-line
operation word are used to encode an M68000 family effective addressing mode (refer to
M68000PM/AD,
M68000 Family Programmer’s Reference Manual
).
The second word of the cpScc instruction format contains the coprocessor condition
selector field in bits 5–0. Bits 15–6 of this word are reserved by Motorola and should be
zero to ensure compatibility with future M68000 products. This word is written to the
condition CIR to initiate execution of the cpScc instruction.
If the coprocessor requires additional information to evaluate the condition, the instruction
can include extension words to provide this information. The number of these extension
words, which follow the word containing the coprocessor condition selector field, is
determined by the coprocessor design.
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